{"group":"cpu_flags_arm","uses":[{"description":"Use the AES cryptography instruction set","group":"cpu_flags_arm","isdefault":false,"use":"aes"},{"description":"Use the Advanced SIMD dot product instructions","group":"cpu_flags_arm","isdefault":false,"use":"asimddp"},{"description":"Use the CRC32 instruction set","group":"cpu_flags_arm","isdefault":false,"use":"crc32"},{"description":"Use the enhanced DSP instructions (ARMv*E and ARMv6+)","group":"cpu_flags_arm","isdefault":false,"use":"edsp"},{"description":"Use the AArch64 Int8 matrix multiplication instructions","group":"cpu_flags_arm","isdefault":false,"use":"i8mm"},{"description":"Use the iwMMXt instruction set","group":"cpu_flags_arm","isdefault":false,"use":"iwmmxt"},{"description":"Use the iwMMXt2 instruction set","group":"cpu_flags_arm","isdefault":false,"use":"iwmmxt2"},{"description":"Use the NEON (ASIMD) instruction set","group":"cpu_flags_arm","isdefault":false,"use":"neon"},{"description":"Use the SHA-1 cryptography instruction set","group":"cpu_flags_arm","isdefault":false,"use":"sha1"},{"description":"Use the SHA-2 cryptography instruction set","group":"cpu_flags_arm","isdefault":false,"use":"sha2"},{"description":"Use the SM4 cryptography instruction set","group":"cpu_flags_arm","isdefault":false,"use":"sm4"},{"description":"Use the Scalable Vector Extension instruction set","group":"cpu_flags_arm","isdefault":false,"use":"sve"},{"description":"Use the Scalable Vector Extension 2 instruction set","group":"cpu_flags_arm","isdefault":false,"use":"sve2"},{"description":"Enable Thumb instruction set (ARMv*T and ARMv6+)","group":"cpu_flags_arm","isdefault":false,"use":"thumb"},{"description":"Enable Thumb-2 instruction set (ARMv*T2 and ARMv7+)","group":"cpu_flags_arm","isdefault":false,"use":"thumb2"},{"description":"Use instructions added in ARMv4","group":"cpu_flags_arm","isdefault":false,"use":"v4"},{"description":"Use instructions added in ARMv5","group":"cpu_flags_arm","isdefault":false,"use":"v5"},{"description":"Use instructions added in ARMv6","group":"cpu_flags_arm","isdefault":false,"use":"v6"},{"description":"Use instructions added in ARMv7","group":"cpu_flags_arm","isdefault":false,"use":"v7"},{"description":"Use instructions added in ARMv8","group":"cpu_flags_arm","isdefault":false,"use":"v8"},{"description":"Use the VFP version 2 instruction set","group":"cpu_flags_arm","isdefault":false,"use":"vfp"},{"description":"Indicate that the FPU has 32 64-bit VFP (v3+) registers (16 otherwise)","group":"cpu_flags_arm","isdefault":false,"use":"vfp-d32"},{"description":"Use the VFP version 3 instruction set","group":"cpu_flags_arm","isdefault":false,"use":"vfpv3"},{"description":"Use the VFP version 4 instruction set","group":"cpu_flags_arm","isdefault":false,"use":"vfpv4"}]}