{"group":"cpu_flags_x86","uses":[{"description":"Use the 3DNow! instruction set","group":"cpu_flags_x86","isdefault":false,"use":"3dnow"},{"description":"Use the Enhanced 3DNow! instruction set","group":"cpu_flags_x86","isdefault":false,"use":"3dnowext"},{"description":"Enable support for Intel's AES instruction set (AES-NI)","group":"cpu_flags_x86","isdefault":false,"use":"aes"},{"description":"Adds support for Advanced Vector Extensions instructions","group":"cpu_flags_x86","isdefault":false,"use":"avx"},{"description":"Adds support for Advanced Vector Extensions 2 instructions","group":"cpu_flags_x86","isdefault":false,"use":"avx2"},{"description":"Use AVX-512 Fused Multiply-Accumulate Packed Single Precision instruction set","group":"cpu_flags_x86","isdefault":false,"use":"avx512_4fmaps"},{"description":"Use AVX-512 Vector Neural Network Instructions Word Variable Precision","group":"cpu_flags_x86","isdefault":false,"use":"avx512_4vnniw"},{"description":"Use AVX-512 BFloat16 instruction set","group":"cpu_flags_x86","isdefault":false,"use":"avx512_bf16"},{"description":"Use AVX-512 Bit Algorithms instruction set","group":"cpu_flags_x86","isdefault":false,"use":"avx512_bitalg"},{"description":"Use general-purpose numeric operations for 16-bit half-precision instruction set","group":"cpu_flags_x86","isdefault":false,"use":"avx512_fp16"},{"description":"Use AVX-512 Vector Bit Manipulation Instructions 2","group":"cpu_flags_x86","isdefault":false,"use":"avx512_vbmi2"},{"description":"Use vector neural network instructions for 8- and 16-bit multiply-add operations","group":"cpu_flags_x86","isdefault":false,"use":"avx512_vnni"},{"description":"Use AVX-512 Intersect instruction set","group":"cpu_flags_x86","isdefault":false,"use":"avx512_vp2intersect"},{"description":"Use AVX-512 Vector Population Count Doubleword and Quadword instruction set","group":"cpu_flags_x86","isdefault":false,"use":"avx512_vpopcntdq"},{"description":"Use AVX-512 byte- and word instructions","group":"cpu_flags_x86","isdefault":false,"use":"avx512bw"},{"description":"Use AVX-512 conflict detection instructions","group":"cpu_flags_x86","isdefault":false,"use":"avx512cd"},{"description":"Use AVX-512 double- and quad-word instructions","group":"cpu_flags_x86","isdefault":false,"use":"avx512dq"},{"description":"Use AVX-512 exponential and reciprocal instructions","group":"cpu_flags_x86","isdefault":false,"use":"avx512er"},{"description":"Adds support for AVX-512 Foundation instructions","group":"cpu_flags_x86","isdefault":false,"use":"avx512f"},{"description":"Use AVX-512 Integer Fused Multiply-Add instruction set","group":"cpu_flags_x86","isdefault":false,"use":"avx512ifma"},{"description":"Use AVX-512 prefetch instructions","group":"cpu_flags_x86","isdefault":false,"use":"avx512pf"},{"description":"Use AVX-512 vector byte manipulation instructions","group":"cpu_flags_x86","isdefault":false,"use":"avx512vbmi"},{"description":"Use AVX-512 vector-length instructions","group":"cpu_flags_x86","isdefault":false,"use":"avx512vl"},{"description":"Adds support for F16C instruction set for converting between half-precision and single-precision floats","group":"cpu_flags_x86","isdefault":false,"use":"f16c"},{"description":"Use the Fused Multiply Add 3 instruction set ([fma] in cpuinfo)","group":"cpu_flags_x86","isdefault":false,"use":"fma3"},{"description":"Use the Fused Multiply Add 4 instruction set","group":"cpu_flags_x86","isdefault":false,"use":"fma4"},{"description":"Use the MMX instruction set","group":"cpu_flags_x86","isdefault":false,"use":"mmx"},{"description":"Use the Extended MMX instruction set (a subset of SSE) ([mmxext] or [sse] in cpuinfo)","group":"cpu_flags_x86","isdefault":false,"use":"mmxext"},{"description":"Use VIA padlock instructions ([phe] in cpuinfo)","group":"cpu_flags_x86","isdefault":false,"use":"padlock"},{"description":"Use Carry-less Multiplication instructions ([pclmulqdq] in cpuinfo)","group":"cpu_flags_x86","isdefault":false,"use":"pclmul"},{"description":"Enable popcnt instruction support ([abm] or [popcnt] in cpuinfo)","group":"cpu_flags_x86","isdefault":false,"use":"popcnt"},{"description":"Use the RDRAND instruction for generating random numbers","group":"cpu_flags_x86","isdefault":false,"use":"rdrand"},{"description":"Use the SHA-NI instruction set","group":"cpu_flags_x86","isdefault":false,"use":"sha"},{"description":"Use the SSE instruction set","group":"cpu_flags_x86","isdefault":false,"use":"sse"},{"description":"Use the SSE2 instruction set","group":"cpu_flags_x86","isdefault":false,"use":"sse2"},{"description":"Use the SSE3 instruction set ([pni] in cpuinfo, NOT ssse3)","group":"cpu_flags_x86","isdefault":false,"use":"sse3"},{"description":"Enable SSE4.1 instruction support","group":"cpu_flags_x86","isdefault":false,"use":"sse4_1"},{"description":"Enable SSE4.2 instruction support","group":"cpu_flags_x86","isdefault":false,"use":"sse4_2"},{"description":"Enable SSE4a instruction support","group":"cpu_flags_x86","isdefault":false,"use":"sse4a"},{"description":"Use the SSSE3 instruction set (NOT sse3\/pni)","group":"cpu_flags_x86","isdefault":false,"use":"ssse3"},{"description":"Use Vector Carry-Less Multiplication of Quadwords instruction set","group":"cpu_flags_x86","isdefault":false,"use":"vpclmulqdq"},{"description":"Enable the XOP instruction set","group":"cpu_flags_x86","isdefault":false,"use":"xop"}]}