- 3dnow
- Use the 3DNow! instruction set
- 3dnowext
- Use the Enhanced 3DNow! instruction set
- aes
- Enable support for Intel's AES instruction set (AES-NI)
- amx_bf16
- Use Advanced Matrix Extensions tile computational operations on bfloat16 numbers
- amx_int8
- Use Advanced Matrix Extensions tile computational operations on 8-bit integers
- amx_tile
- Use Advanced Matrix Extensions tile architecture support
- avx
- Adds support for Advanced Vector Extensions instructions
- avx2
- Adds support for Advanced Vector Extensions 2 instructions
- avx512_4fmaps
- Use AVX-512 Fused Multiply-Accumulate Packed Single Precision instruction set
- avx512_4vnniw
- Use AVX-512 Vector Neural Network Instructions Word Variable Precision
- avx512_bf16
- Use AVX-512 BFloat16 instruction set
- avx512_bitalg
- Use AVX-512 Bit Algorithms instruction set
- avx512_fp16
- Use general-purpose numeric operations for 16-bit half-precision instruction set
- avx512_vbmi2
- Use AVX-512 Vector Bit Manipulation Instructions 2
- avx512_vnni
- Use vector neural network instructions for 8- and 16-bit multiply-add operations
- avx512_vp2intersect
- Use AVX-512 Intersect instruction set
- avx512_vpopcntdq
- Use AVX-512 Vector Population Count Doubleword and Quadword instruction set
- avx512bw
- Use AVX-512 byte- and word instructions
- avx512cd
- Use AVX-512 conflict detection instructions
- avx512dq
- Use AVX-512 double- and quad-word instructions
- avx512er
- Use AVX-512 exponential and reciprocal instructions
- avx512f
- Adds support for AVX-512 Foundation instructions
- avx512ifma
- Use AVX-512 Integer Fused Multiply-Add instruction set
- avx512pf
- Use AVX-512 prefetch instructions
- avx512vbmi
- Use AVX-512 vector byte manipulation instructions
- avx512vl
- Use AVX-512 vector-length instructions
- avx_vnni
- Use AVX (VEX-encoded) versions of the Vector Neural Network Instructions
- bmi1
- Enable the first group of advanced bit manipulation extensions (ANDN, BEXTR, BLSI, BLSMSK, BLSR, TZCNT)
- bmi2
- Enable the second group of advanced bit manipulation extensions (BZHI, MULX, PDEP, PEXT, RORX, SARX, SHLX, SHRX)
- f16c
- Adds support for F16C instruction set for converting between half-precision and single-precision floats
- fma3
- Use the Fused Multiply Add 3 instruction set ([fma] in cpuinfo)
- fma4
- Use the Fused Multiply Add 4 instruction set
- mmx
- Use the MMX instruction set
- mmxext
- Use the Extended MMX instruction set (a subset of SSE) ([mmxext] or [sse] in cpuinfo)
- padlock
- Use VIA padlock instructions ([phe] in cpuinfo)
- pclmul
- Use Carry-less Multiplication instructions ([pclmulqdq] in cpuinfo)
- popcnt
- Enable popcnt instruction support ([abm] or [popcnt] in cpuinfo)
- rdrand
- Use the RDRAND instruction for generating random numbers
- sha
- Use the SHA-NI instruction set
- sse
- Use the SSE instruction set
- sse2
- Use the SSE2 instruction set
- sse3
- Use the SSE3 instruction set ([pni] in cpuinfo, NOT ssse3)
- sse4_1
- Enable SSE4.1 instruction support
- sse4_2
- Enable SSE4.2 instruction support
- sse4a
- Enable SSE4a instruction support
- ssse3
- Use the SSSE3 instruction set (NOT sse3/pni)
- vpclmulqdq
- Use Vector Carry-Less Multiplication of Quadwords instruction set
- xop
- Enable the XOP instruction set